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In this work, we present a new architecture for soft-decision Reed–Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high nuer of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the loion of the errors inside the syols and the powers of α that identify the positions of the

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Accelerate Energy Efficient SoC designs - Dolphin Design

Power-gating techniques enable to switch-off (independently) the power-supply of parts of the circuit that are not in use to reduce leakage power. The support for these design techniques requires the usage of specific cells not included in regular standard cell libraries.

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dblp: ICACCI 2018

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Staff Profile - Engineering, School of - Newcastle University

Digital phase locked loop for power conversion ASICs. In: Proceedings of the European Conference on Design Automation with the European Event in ASIC Design, Feb 22-25 1993. 1993, Paris, Fr: Publ by IEEE, Los Alamitos, CA, USA. B.S. Sharif,D.T

dblp: Jun Yang

Jun Yang 0006 — Southeast University, National ASIC system Engineering Research Center, Nanjing, China Jun Yang 0007 — Nagoya University Jun Yang 0008 — Northeastern University, Shenyang Jun Yang 0009 — Xi''an Jiaotong University, Xi''an, China 0010